Stencil mask for high - and ultrahigh-energy implantation

ABSTRACT

A stencil mask for high - and ultrahigh-energy implantation of semiconductor wafers has a substrate with implantation openings through which the implantation energy can be projected onto a wafer that will be implanted. The critical dimension of the implantation openings is defined in a manner dependent on the respective implantation energy.

BACKGROUND OF THE INVENTION

[0001] Field of the Invention

[0002] The invention relates to a stencil mask for high- andultrahigh-energy implantation that has implantation openings in asubstrate through which the implantation energy can be projected onto awafer that will be implanted. The invention also relates to a method setup for fabricating a stencil mask of this type.

[0003] New kinds of vertical high-voltage silicon components (those thatwithstand voltages greater than 300 V) require vertical, pillar-type andfinely patterned doping regions in the epitaxial drift zone. Theseso-called compensation components reduce the on resistance by up to oneorder of magnitude. To fabricate such vertical finely patterned dopingregions, from today's standpoint high-energy implantation (up to 25 MeVboron) using silicon stencil masks appears to be the only methodactually suitable in order both to expand the manufacturing capacity andto reduce the costs to a significant extent.

[0004] From a technical standpoint, fabricating suitable stencil masksfor high-energy implantation is problematic since compensationcomponents are based on the principle of balanced doping between thevertical compensation pillars and the basic doping of the epitaxiallayer. Deviations in this balance by a few percent already lead to adrastic reduction in the blocking capability. Stencil masks are usuallyfabricated by phototechnological patterning of SOI wafers and subsequenttrench etching. In this case, the trench depth for a 600 V component isapproximately 35 μm. Dry-chemical etching machines which arecommercially available nowadays achieve a reproducibility of thesidewall inclination of the etched trenches of about 0.5° to 1.0° on an8 inch wafer. The conditions and the problems of such a relatively thickstencil mask M are illustrated in the form of a diagrammatic crosssection in the accompanying FIG. 7. FIG. 7 illustrates how theimplantation opening diameter 2r, which is to be regarded as thecritical dimension CD, changes from its target value 2r_(target) to anactual value 2r_(ACTUAL) if the angle α_(trench) which specifies thesidewall inclination increases by the value Δα_(trench). The effectiveCD dimension specifies a so-called “projected range” Rp, which isequivalent to a given implantation energy E.

[0005] Table 1 illustrated in the accompanying FIG. 8 shows thedependence of the dose fluctuation of the implantation energy relativeto the target dose in the event of deviation of the trench sidewallangle α_(trench) in the stencil mask M in accordance with FIG. 7.

[0006] The cumulative fluctuation (error propagation) lies in the rangefrom ±40 to 60% of the target dose. Cumulative fluctuations of ±10 to15% are acceptable for the device (compensation component) to befabricated. This value already takes account of fluctuations in theresist dimension and in the doping of the epitaxial layer.

[0007] The crucial disadvantage of the stencil mask patterned inaccordance with FIG. 7 is that the effective CD dimensions associatedwith the respective implantation energies are only controlled by theupper opening dimension of the trench and the trench angle α_(trench).In particular for high implantation energies and correspondingly thickstencil masks, even slight deviations from the ideal trench angle giverise to a major effect on the critical dimension CD.

[0008] To date, such compensation components have been exclusivelyfabricated using the so-called construction technique:

[0009] First an n-doped epitaxial layer having a thickness of severalmicrometers is deposited on the substrate. Using a resist mask, a p-typedoping is subsequently introduced by a low-energy implantation. In thisconnection, particular attention must be paid to the accuracy of theresist dimension of the resist mask since this is the parameter thatdetermines the number of implanted ions, and consequently, the balancebetween the p-type and the n-type doping. The whole process, includingepitaxial deposition, phototechnology and implantation, is repeateduntil the pillar height corresponding to the required withstand voltagehas been constructed. The final sub-process includes a diffusion stepthat causes the implantation regions to diffuse together vertically.

[0010] Stencil masks are currently used primarily for ion projectionlithography. In this technique, only very low-energy ions are used. Theproblem of fluctuation of trench angles in the case of very deeptrenches does not arise in this case, since the silicon mask only has athickness of 3.0 μm. The dimensionally accurate upper part of the trenchextends merely to a depth of 150 nm.

SUMMARY OF THE INVENTION

[0011] It is accordingly an object of the invention to provide a stencilmask for high- and ultrahigh-energy implantation and a method forfabricating the stencil mask which overcome the above-mentioneddisadvantages of the prior art apparatus and methods of this generaltype.

[0012] Following what has been said above, it is an object of theinvention to provide a stencil mask that is suitable for a high- andultrahigh-energy implantation and that significantly reduces thefluctuations shown in Table 1 (FIG. 8). Thus, it is an object of theinvention to enable the development of a high-energy implantationtechnology for such compensation components in an expedient manner.

[0013] In order to achieve the above stated object, the inventionproposes departing from the concept of the simple stencil mask in whichthe implantation openings are defined and formed for all energies byusing a CD dimension (Critical Dimension) and a single trench etchingprocess, and instead defining a dedicated dimensionally accurate maskfor each implantation energy. In the case of this mask, the criticaldimension of the implantation openings is defined in a manner dependenton the respective implantation energy. In a particular embodiment, astencil mask is composed of a plurality of individual dimensionallyaccurate masks, with the result that this combined stencil mask issuitable for different implantation energies. The critical dimension ofthe implantation openings present in a plurality of steps or stages arein each case coordinated with the required implantation energy.

[0014] Instead of this, however, it is also possible to provide adedicated dimensionally accurate mask for each implantation energy andto use the mask in each case for an implantation with a specific energy.In the event of a changeover of the energy, the mask is changed, too. Byway of example, for a compensation component constructed from fivelayers, it is then necessary to fabricate five separate masks withopenings whose critical dimension CD is in each case coordinated withthe energy used for the implantation.

[0015] Preferably, the stencil mask is constructed on an SOI (Silicon onInsulator) base material or is composed of such an SOI base material.

[0016] The following method is particularly advantageously appropriatefor fabricating a stencil mask for the high- and ultrahigh-energyimplantation:

[0017] I. Providing an SOI base material with an SOI layer thicknessadapted to the respective ion penetration depth, for example 5 μm for 3MeV boron, 35 μm for 20 MeV boron.

[0018] II. Etching retrograde openings from the front side of the SOIwafer as far as the SOI oxide layer. This means that for a stencil mask,for example, for a 20 MeV implantation, the first 1.2 μm (+ safetymargins) of this opening (trench) must be exact. The rest of the trenchneed only satisfy very undemanding requirements.

[0019] III. The mask is made transparent from the rear side bywet-chemical etching, for example.

[0020] IV. The stencil mask is used as an implantation mask, forexample, by bonding or precisely positioning the mask in front of thewafer that will be implanted in such a way that the front side of themask points in the direction of the wafer that will be implanted.

[0021] With the foregoing and other objects in view there is provided,in accordance with the invention, a stencil mask for high- andultrahigh-energy implantation of semiconductor wafers. The stencil maskincludes a substrate formed with implantation openings through whichions that will be implanted onto a wafer can be projected with aimplantation energy onto the wafer. Each of the implantation openingshave a diameter that is defined in a manner dependent on theimplantation energy.

[0022] In accordance with an added feature of the invention, thesubstrate forms an individual stencil mask; and each of the implantationopenings have a single diameter for the implantation energy.

[0023] In accordance with an additional feature of the invention, thesubstrate forms a single stencil mask with a plurality of dimensionallyaccurate individual stencil masks; and each of the plurality of thedimensionally accurate individual stencil masks is formed withimplantation openings having diameters that are coordinated with animplantation energy of a respective implantation step of a multi-stepimplantation with different implantation energies.

[0024] In accordance with another feature of the invention, thesubstrate is constructed on an SOI base material.

[0025] In accordance with a further feature of the invention, thesubstrate is made from an SOI base material.

[0026] With the foregoing and other objects in view there is provided,in accordance with the invention, a method for fabricating a stencilmask for high-and ultrahigh-energy implantation that includes steps of:constructing a stencil mask having implantation openings formed therein,the openings being provided for projecting ions therethrough that willbe implanted onto a wafer; and forming the implantation openings withdiameters being determined by a respective implantation energy of theions that will be projected therethrough.

[0027] In accordance with an added mode of the invention, the stencilmask is constructed by performing the steps of: forming a first oxidelayer, which is accurately dimensionally prepatterned, on a siliconlayer of a silicon-on-insulator wafer having a silicon-on-insulator basematerial by performing a step selected from the group consisting of adepositing step and a growing step, and subsequently performing a trenchetching of the silicon layer using an oxide layer of thesilicon-on-insulator wafer as a stop and using oxide regions on thesilicon layer as dimensionally accurate hard masks.

[0028] In accordance with an additional mode of the invention, thestencil mask is constructed such that the implantation openings have aplurality of different diameters by: performing a plurality of stepsthat are each either a depositing step or a growing step to construct aplurality of silicon layers and a plurality of dimensionally accuratelypatterned oxide layers such that each one the oxide layers is locatedabove a respective one of the silicon layers, such that each one of theoxide layers has implantation openings that are centered in relation torespective implantation openings in others of the oxide layers, and suchthat the diameters of the implantation openings in each respective oneof the oxide layers are larger than the diameters of the implantationopenings in the oxide layers below the respective one of the oxidelayers. Subsequently, starting from a topmost one of the oxide layers,and stopping on the oxide layer of the silicon-on-insulator wafer, atrench etching is performed through each one of the silicon layers inwhich all of the patterned oxide layers act as dimensionally accuratehard masks lying one above another.

[0029] In accordance with another mode of the invention, the methodincludes: subsequently patterning the silicon-on-insulator wafer from arear side of the wafer; forming large window openings by performing astep selected from the group consisting of wet-chemical etching anddry-chemical etching through the silicon layer and the oxide layer ofthe silicon-on insulator wafer; and providing the stencil mask with afront side that can positioned over a semiconductor wafer that will beimplanted by configuring the stencil mask in a flipped position.

[0030] In accordance with a further mode of the invention, the stencilmask is constructed by: a) applying and dimensionally accuratelypatterning a first mask on a silicon layer of an SOI wafer, the firstmask being selected from the group consisting of a hard mask and aresist mask, b) through openings in the first mask, performing a trenchetching in the silicon layer of the SOI wafer, c) subsequently closingoff each etched trench with a plug and after removing the first mask,leveling a surface of the silicon layer, d) performing steps a) - c) asoften as necessary, and e) patterning a rear side of the SOI wafer toform large windows by performing a step selected from the groupconsisting of a wet-chemical etching step and a dry-chemical etchingstep.

[0031] In accordance with a further added mode of the invention, thestencil mask is constructed using a stepped trench etching of a siliconlayer of an SOI base material in a desired target thickness, byperforming the following steps: Applying and patterning a first mask onthe silicon layer of the SOI wafer. The first mask is either a resistmask or a hard mask. Subsequently, forming a trench having trench wallsand a trench bottom by performing a first trench etching into thesilicon layer down to a first depth and applying an oxide layer to coverthe trench walls and the trench bottom. Subsequently etching the oxidelayer at the trench bottom to produce a dimensionally accurate openingleading to the silicon layer. Subsequently performing a second trenchetching in the trench down to a second selected target depth anddepositing a further oxide layer in the trench. Subsequently, performinga further spacer etching of the further oxide layer at a trench bottom.Performing a renewed trench etching as far as an SOI oxide of the SOIbase material. Subsequently, patterning a wafer rear side by performingeither a wet-chemical etching step or a dry-chemical etching to formlarge windows, and wet-chemically etching the SOI oxide and side walloxides of the stepped trench.

[0032] Other features which are considered as characteristic for theinvention are set forth in the appended claims.

[0033] Although the invention is illustrated and described herein asembodied in a stencil mask for high- and ultrahigh-energy implantation,it is nevertheless not intended to be limited to the details shown,since various modifications and structural changes may be made thereinwithout departing from the spirit of the invention and within the scopeand range of equivalents of the claims.

[0034] The construction and method of operation of the invention,however, together with additional objects and advantages thereof will bebest understood from the following description of specific embodimentswhen read in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0035]FIG. 1 is a diagrammatic cross sectional view of a firstembodiment of a stencil mask for high- and ultrahigh-energyimplantation;

[0036]FIG. 2 is a diagrammatic cross sectional view of a stencil maskthat is positioned above a device wafer during an implantation;

[0037]FIG. 3 is a diagrammatic cross sectional view of a secondembodiment of a stencil mask;

[0038] FIGS. 4A-4E are cross-sectional illustrations for explaining afirst exemplary embodiment of a method for fabricating a stencil mask;

[0039] FIGS. 5A-5E are cross-sectional illustrations through an SOIwafer for explaining a second exemplary embodiment of a method forfabricating a stencil mask;

[0040] FIGS. 6A-6D are cross-sectional illustrations through an SOIwafer for explaining individual steps of a third exemplary embodiment ofa method for fabricating a stencil mask;

[0041]FIG. 7 is a diagrammatic cross section through a conventionalstencil mask; and

[0042]FIG. 8 is a table showing that alterations of the implantationdose depend on a variation of the target angle.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0043] Referring now to the figures of the drawing in detail and first,particularly, to FIG. 1 thereof, there is shown a diagrammatic crosssectional view of a first embodiment of an inventive stencil mask 1.FIG. 2 shows the stencil mask 1 positioned above a device wafer 20. Thestencil mask 1 shown in FIG. 1 is characterized by defining the criticaldimension CD (diameter) of an implantation opening 2 (only one openingis shown for the purpose of simplification) in a manner dependent on adesired implantation energy. An SOI base material is used as the initialbasis for fabricating the stencil mask 1. The SOI base material includesa first SI layer 10, an oxide layer 11 and a second SI layer 12, whosethickness is adapted to the respective ion penetration depth during theion implantation of a target wafer 20 as shown in FIG. 2. This thicknessis, for example, 5 μm for 3 MeV boron and 35 μm for 20 MeV boron.

[0044] During the fabrication of the stencil mask 1, first retrogradeopenings 2 are etched from the front side V as far as the oxide layer 11by using a dry- or wet-etching process (arrow A). This means that theetching A has to be exactly dimensionally accurate only at the beginning(depth d). By way of example, the etched trench must be exact for d=1.2μm for a 20 MeV implantation mask. The dimension of the rest of thetrench forming the opening 2 need only satisfy very undemandingrequirements. Afterward, the stencil mask 1 is made transparent from therear side R by wet-chemical etching, for example. In other words, on therear side R, large windows are opened in the first SI layer 10 and inthe oxide layer 11 of the SOI wafer.

[0045] As shown in FIG. 2, the mask 1 is fixed as an implantation mask,for example, by bonding or by precisely positioning the mask in front ofthe device wafer 20. When the mask 1 is used, the front side V of themask 1 is located above the device wafer 20 to be implanted. FIG. 2shows a bonding layer 13 with which the stencil mask 1 is adhesivelybonded on the device wafer 20. Implantation energy E is applied fromabove. In this case, as mentioned, the critical dimension CD, i.e. theclearance of the opening 2 at the distance d from the front side V ofthe mask, is defined in a manner dependent on the implantation energy E.

[0046] In a further embodiment of the inventive stencil mask, aplurality of dimensionally accurate masks whose critical dimension CD isin each case coordinated with the respective implantation energy to beused are combined to form a single stencil mask 1.

[0047] Such a combined stencil mask 1 will now be explained withreference to FIG. 3. The stencil mask 1, which is illustrated in adiagrammatic cross sectional view in FIG. 3, has an associated CDdimension CD1, CD2, CD3 and CD4 for each implantation energy, that is tosay, for each projected range Rp1, Rp2, Rp3, and Rp4. CD1 is the preciseopening width for an implantation with a first energy. CD2 is theprecise opening width for an implantation with a second energy. CD3 isthe precise opening width for an implantation with a third energy. CD4is the precise opening width for an implantation with a fourth energy.Lying between these precisely defined openings are non-critical regionswhich are permitted to be subject to large fluctuations. For theimplantation operation, the stencil mask shown in FIG. 3 is to bepositioned, or fixed positionally accurately, with its front side Vabove a device wafer.

[0048]FIG. 3 also illustrates that the implantation profile P_(I) of ahigh-energy implantation is configured such that the majority of theimplanted dose lies in the region of the projected range Rp.

[0049] The fourth column, +/−2 sigma, of table 2 shown below specifiesthe depth region in which 95.4% of the implanted dose is deposited. Thisis then, the distance at which the dimensional accuracy of therespective implantation opening must be ensured. If this is the case,then the abovementioned 95.4% of the dose has been implanted exactly.TABLE 2 The projected range Rp and the first moment of the iondistribution after the implantation with different energies Rp verticalDelta Rp +/−2 Sigma [μm] [μm] [μm] 3 MeV 3.7 0.2 0.8 9 MeV 9.9 0.25 1.015 MeV 17.4 0.25 1.0 20 MeV 24.8 0.30 1.2

[0050] The accuracy can be increased further by appropriate measures(expanding the exact region). The structures proposed must additionallybe adapted to the experimental specifications with safety margins atdifferent locations. It is important in this connection to exactly knowthe penetration depth, or even better to know the exact implantationprofile of the ions before fabricating the mask. The dimensionallyaccurate opening must, of course, be incorporated in the correct overalldepth.

[0051] The combined stencil mask which is shown in FIG. 3 and describedabove has the following advantages:

[0052] shallow etchings with a depth in the range from one to a few μmcan be fabricated on the wafer that is used for fabricating the stencilmask, with very small fluctuations with regard to the critical dimensionCD and the trench angle. Consequently, compared with conventionalstencil masks with deep trenches, a significant improvement is producedin the overall accuracy on the mask from the center to the edge; and

[0053] for the same reason, the fluctuation from mask to mask islikewise reduced.

[0054] In the case of conventional stencil masks, there are in principleonly two parameters available during the fabrication of the mask. Theyare the CD dimension of the upper opening and the trench angle. However,it is precisely the trench angle that is essentially pre-determined bythe etching chemistry and can be set in a defined manner only with verygreat difficulty. An added difficulty is the fact that exact control ofthe trench angle over large depths is possible only with the lowaccuracy of greater than ±0.5°.

[0055] Exemplary embodiments of a method used for fabricating a stencilmask according to the invention are described below.

[0056] FIGS. 4A-4E show method steps of a first exemplary embodiment ofa method for fabricating a stencil mask 1, for example, the mask thathas been described above with reference to FIG. 3.

[0057] In accordance with FIG. 4A, the starting point is formed by anSOI base material including a first SI layer 10, an oxide layer 11 and asecond SI layer 12 in this order. An oxide layer 13 is deposited abovethe upper (second) SI layer 12 and patterned dimensionally accurately.“Dimensionally accurately” means that the width of the patterned openingof the oxide layer 13 defines a first critical dimension (CD1)(also seeFIG. 3, for example).

[0058] In accordance with FIG. 4B, a further SI layer 14 is applied onthe oxide layer 13 and a further oxide layer 15 is applied above the SIlayer 14. The further oxide layer 15, for its part, is patterneddimensionally accurately such that the width of its opening specifies asecond critical dimension (CD2).

[0059] In accordance with FIG. 4C, the step illustrated in FIG. 4B isrepeated, a further SI layer 16 is deposited and a third oxide layer 17is deposited above the SI layer and is patterned dimensionallyaccurately in such a way that the width of the opening formed in theoxide layer 17 defines a third critical dimension CD3.

[0060] It should be noted here that the respective projected ranges aredefined by the thicknesses of the respective SI layers 12, 14, 16.

[0061] In accordance with FIG. 4D, a silicon etching (trench etching) isthen effected, during which the oxide regions 13, 15, 17 in each planeserve as dimensionally accurate hard masks, as far as the etching stopby the oxide layer 11 of the SOI base material (arrow A1).

[0062] In accordance with FIG. 4E, the stencil mask 1 is completed bypatterning the rear side R of the wafer. In this case, large windows areopened by wet-chemical or dry-chemical etching (silicon and oxide)(illustrated by the arrows A2), thereby finishing the fabrication of theimplantation opening 2 of the stencil mask 1. The structure shown inFIG. 4E, that is to say the stencil mask 1, is flipped, that is to saybrought to a position in which its rear side R is positioned above adevice wafer (not shown) and used as an implantation mask.

[0063] FIGS. 5A-5E show method steps of a construction method forfabricating a stencil mask 1. This method is an alternative to theconstruction method shown in FIGS. 4A-4E. Once again an SOI basematerial including a first SI layer 10, an oxide layer 11 and a secondSI layer 12 serves as the starting wafer for fabricating a stencil mask.The surface of the upper, that is to say second, SI layer 12 is coveredwith a resist or hard mask 8 as shown in FIG. 5A and the mask ispatterned dimensionally accurately. Here again, dimensionally accuratelymeans that the dimension of the opening width of the patterned resist orhard mask 8 complies with a critical dimension for the implantationopening, for example CD3. Afterward, a downwardly widening first trench21 is etched through the opening of the resist or hard mask 8.

[0064] In accordance with FIG. 5B, the first trench 21 is closed with aplug 7, for example a BPSG plug. The hard or resist mask 8 is removed,and the surface of the trench 21 that is closed with the plug 7 and thesurface of the silicon layer 12 are planarized. It should be mentionedthat planar surfaces can be obtained automatically with the BPSG plugtechnique given suitable process control, so that the planarization stepcan then be omitted.

[0065] In accordance with FIG. 5C, a further SI layer 14 is deposited orgrown on the upper silicon layer 12 of the SOI base material. Thefurther SI layer is then covered with a resist or hard mask 9 that issubsequently patterned dimensionally accurately. Dimensionallyaccurately in this case means that the opening width of the openingformed in the resist or hard mask 9 must comply with a second criticaldimension, for example, CD2 of the implantation opening of the stencilmask. A second downwardly widening trench 22 is then etched, in whichthe plug 7 serves as an etching stop. The steps shown in FIGS. 5A to 5Ccan be repeated, as a result of which further layers with further plugscan be fabricated.

[0066] Afterward, in accordance with FIG. 5D, the rear side R of thewafer is patterned using a wet- or dry-chemical silicon etching, as aresult of which large windows are formed in the bottommost SOI siliconlayer 10.

[0067] In accordance with FIG. 5E, the SOI oxide 11 and the plug 7 orthe plugs are then removed from the rear side using a wet-chemical oxideetching, as a result of which the implantation opening 2 is completed.For its use for a high- or ultrahigh-energy implantation, the stencilmask 1 illustrated in FIG. 5E is positioned, or fixed positionallyaccurately, with its front side V above a device wafer.

[0068] The alternative construction methods for a stencil mask that areillustrated in FIGS. 4A-4E and 5A-5E and described above use repeatedsilicon depositions in conjunction with repeated dimensionally accurateoxide or silicon etchings. The mask is constructed step by step on anSOI base material.

[0069] Assuming a reasonable service life, the stencil masks are notcost-limited. That is to say, it is possible to permit significantlymore costly processes than in the case of a product wafer process sincethe masks are reused very often and the fabrication costs are thusdistributed uniformly between all of the wafers fabricated using thismask.

[0070] For reasons of thermal stability, preference should be given tofabrication variants that do not require mixing of materials in the caseof the finished mask. That is to say that masks made of pure silicon, asin the exemplary embodiment shown in FIGS. 5A-5E and as described above,are to be preferred over those that include layer sequences of oxide andsilicon.

[0071] In the case of the second exemplary embodiment of theconstruction method that is illustrated in FIGS. 5A-5E and describedabove, the deposited silicon can also be grown epitaxially—at a lowtemperature. This likewise has considerable advantages for the thermalstability of the stencil mask fabricated. Disturbances to thecrystallinity in the region of the oxide plugs play only aninsignificant part since these regions are etched again in the nextconstruction step.

[0072] The third exemplary embodiment of a fabrication method for astencil mask according to the invention as described below withreference to FIGS. 6A-6D does not use a construction technique of thekind used in the exemplary embodiments described with reference to FIGS.4A-4E and 5A-5E, but rather uses a stepped trench etching. The startingmaterial used is once again an SOI wafer including a first silicon layer10, an oxide layer 11 and a second silicon layer 12. In this case, themethod of stepped trench etching corresponding to the third exemplaryembodiment differs from the construction methods described above inprinciple by the fact that the second silicon layer 12 already has thetarget thickness at the beginning of the fabrication process for thestencil mask.

[0073] In accordance with FIG. 6A, a resist or hard mask 8 is appliedabove the second SI layer 12 and is patterned dimensionally accurately.The opening width has the critical dimension CD4. A trench etching downto a first target depth Rp is subsequently effected. An oxide layer 13is subsequently deposited into the trench. The oxide layer covers thebottom and the sidewalls of the trench. The deposited oxide layer mustbe so thick that, after an oxide etching (arrow A) which is illustratedin FIG. 6B and is comparable to a spacer etching, the requireddimensionally accurate opening remains in accordance with the criticaldimension CD3.

[0074] Afterward, in accordance with FIG. 6C, a further trench etchingdown to a second target depth is carried out, a further suitable oxidelayer 15 is deposited and that section of the second oxide layer 15which lies at the bottom of the second trench is etched by a spaceretching, thereby producing a dimensionally accurate opening inaccordance with the critical dimension CD2. A renewed trench etchingwith a stop on the SOI oxide 11 is subsequently effected. Depending onthe required mask thickness of the stencil mask 1 and the requirednumber of stepped critical dimensions CD, this process must be repeateda number of times.

[0075] In accordance with FIG. 6D, the wafer rear side R is patterned bywet- or dry-chemical etching with large windows being opened. The SOIoxide layer 11 and the sidewall oxides 13, 15 are subsequently etchedwet-chemically.

[0076] Consequently, by using the stepped trench etching described, astencil mask 1 with critical dimensions CD4, CD3, CD2 and CD1 whichtaper stepwise is fabricated, as is also illustrated in FIG. 3, forexample. The special feature of the method illustrated in FIGS. 6A-6Djust described is that the dimensional accuracy is set at the requiredlocations not by using phototechnology or the like, but by depositionsor thermal oxidation. In other words, in this case it is particularlyimportant to accurately determine CD dimensions in deep trenches andafterward, building on these measurement results, to be able to apply anauxiliary layer of exact thickness in these trenches. A simpler variantof this method would consist in using base material with incorporatedetching stops, for example, in the form of thin oxide layers. However,in principle this again constitutes a type of construction technique,and consequently it is no longer necessary to effect the costly settingof the dimensional accuracy by using a defined deposition at this point.

[0077] Quite generally, a retrograde trench profile is preferred in allof the embodiments and exemplary embodiments. Other embodimentsinevitably result if a “tapered” trench profile is required. Theembodiments shown or the concept of stepwise dimensional accuracy canalso be applied to other materials, for example, SIC or metals.

I claim:
 1. A stencil mask for high- and ultrahigh-energy implantationof semiconductor wafers, comprising: a substrate formed withimplantation openings through which ions that will be implanted onto awafer can be projected with a implantation energy onto the wafer; eachof said implantation openings having a diameter being defined in amanner dependent on the implantation energy.
 2. The stencil maskaccording to claim 1, wherein: said substrate forms an individualstencil mask; and each of said implantation openings have a singlediameter for the implantation energy.
 3. The stencil mask according toclaim 1, wherein: said substrate forms a single stencil mask with aplurality of dimensionally accurate individual stencil masks; and eachof said plurality of said dimensionally accurate individual stencilmasks is formed with implantation openings having diameters that arecoordinated with an implantation energy of a respective implantationstep of a multi-step implantation with different implantation energies.4. The stencil mask according to claim 1, wherein said substrate isconstructed on an SOI base material.
 5. The stencil mask according toclaim 1, wherein said substrate is made from an SOI base material.
 6. Amethod for fabricating a stencil mask for high-and ultrahigh-energyimplantation, which comprises: constructing a stencil mask havingimplantation openings formed therein, the openings being provided forprojecting ions therethrough that will be implanted onto a wafer; andforming the implantation openings with diameters being determined by arespective implantation energy of the ions that will be projectedtherethrough.
 7. The method according to claim 6, which comprises:constructing the stencil mask by: forming a first oxide layer, which isaccurately dimensionally prepatterned, on a silicon layer of asilicon-on-insulator wafer having a silicon-on-insulator base materialby performing a step selected from the group consisting of a depositingstep and a growing step, and subsequently performing a trench etching ofthe silicon layer using an oxide layer of the silicon-on-insulator waferas a stop and using oxide regions on the silicon layer as dimensionallyaccurate hard masks.
 8. The fabrication method according to claim 7,which comprises: constructing the stencil mask such that theimplantation openings have a plurality of different diameters by:performing a plurality of steps each selected from the group consistingof a depositing step and a growing step to construct a plurality ofsilicon layers and a plurality of dimensionally accurately patternedoxide layers such that each one the oxide layers is located above arespective one of the silicon layers, such that each one of the oxidelayers has implantation openings that are centered in relation torespective implantation openings in others of the oxide layers, and suchthat the diameters of the implantation openings in each respective oneof the oxide layers are larger than the diameters of the implantationopenings in the oxide layers below the respective one of the oxidelayers, and subsequently starting from a topmost one of the oxidelayers, and stopping on the oxide layer of the silicon-on-insulatorwafer, performing a trench etching through each one of the siliconlayers in which all of the patterned oxide layers act as dimensionallyaccurate hard masks lying one above another.
 9. The fabrication methodaccording to claim 8, which comprises: subsequently patterning thesilicon-on-insulator wafer from a rear side of the wafer; forming largewindow openings by performing a step selected from the group consistingof wet-chemical etching and dry-chemical etching through the siliconlayer and the oxide layer of the silicon-on insulator wafer; andproviding the stencil mask with a front side that can positioned over asemiconductor wafer that will be implanted by configuring the stencilmask in a flipped position.
 10. The fabrication method as claimed inclaim 6, which comprises: constructing the stencil mask by: a) applyingand dimensionally accurately patterning a first mask on a silicon layerof an SOI wafer, the first mask being selected from the group consistingof a hard mask and a resist mask, b) through openings in the first mask,performing a trench etching in the silicon layer of the SOI wafer, c)subsequently closing off each etched trench with a plug and afterremoving the first mask, leveling a surface of the silicon layer, d)performing steps a) - c) as often as necessary, and e) patterning a rearside of the SOI wafer to form windows by performing a step selected fromthe group consisting of a wet-chemical etching step and a dry-chemicaletching step.
 11. The fabrication method according to claim 6, whichcomprises: constructing the stencil mask using a stepped trench etchingof a silicon layer of an SOI base material in a desired targetthickness, by: applying and patterning a first mask on the silicon layerof the SOI wafer, the first mask being selected from the groupconsisting of a resist mask and a hard mask, and subsequently forming atrench having trench walls and a trench bottom by performing a firsttrench etching into the silicon layer down to a first depth and applyingan oxide layer to cover the trench walls and the trench bottom, andsubsequently etching the oxide layer at the trench bottom to produce adimensionally accurate opening leading to the silicon layer, andsubsequently performing a second trench etching in the trench down to asecond selected target depth and depositing a further oxide layer in thetrench, and subsequently performing a further spacer etching of thefurther oxide layer at a trench bottom, performing a renewed trenchetching as far as an SOI oxide of the SOI base material, andsubsequently patterning a wafer rear side by performing a step selectedfrom the group consisting of a wet-chemical etching step and adry-chemical etching to form large windows, and wet-chemically etchingthe SOI oxide and side wall oxides of the stepped trench.